With the user-provided target clock period constraint (e.g.
USER GUIDE FOR QUARKXPRESS 9.1 SOFTWARE
The scheduling step of HLS bridges this gap, by assigning the computations in the software to occur in specific clock cycles in hardware. Scheduling: Software programs are written without any notion of a clock or finite state machine (FSM).how many divider units may be used, the number of RAM ports, etc.), as well as the target clock period for the hardware, and other user-supplied constraints.
Allocation: The allocation step defines the constraints on the generated hardware, including the number of hardware resources of a given type that may be used (e.g.The four main steps involved in HLS are allocation, scheduling, binding, and RTL generation, which runs one after another (i.e., binding runs after scheduling is done). While a detailed knowledge of HLS is not required to use LegUp, it is worthwhile to highlight the key steps involved in converting software to hardware. This can help to shorten design cycles, improve design productivity and reduce time-to-market. The underlying motivation for HLS is to raise the level of abstraction for hardware design, by allowing software methodologies to be used to design hardware. The LegUp-generated Verilog can be given to Libero to be programmed on a Microchip FPGA. For LegUp, the input is a C/C++-language program, and the output is a circuit specification in the Verilog hardware description language. High-level synthesis (HLS) refers to the synthesis of a hardware circuit from a software program specified in a high-level language, where the hardware circuit performs the same functionality as the software program.